Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead (ASIC/EDA)

Location: San Jose, California, United States

Salary: $187,000–$270,000 USD annually for the Bay Area, with additional incentive opportunities.

Company

hirify.global is a pure-play FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

• Own static timing analysis flows and timing-modeling methodology across ASIC, custom, semi-custom IP, and FPGA designs.
• Develop and release production-grade design automation flows, regressions, validation, deployment, and workflow automation.
• Modernize characterization flows and onboard timing sign-off into a unified flow environment.
• Partner with design, physical design, technology enablement, reliability, and EDA vendor organizations to define methodology requirements and resolve tool gaps.
• Support live tape-outs by triaging tickets, debugging timing issues, and providing training and documentation.
• Set technical direction and mentor engineers across timing methodology, characterization, circuit simulation, and timing-model generation.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 10+ years of experience in semiconductor design automation, CAD/EDA engineering, ASIC/custom IC design, or a closely related field.
• 10+ years of hands-on experience with STA and timing sign-off methodology, including timing constraints, MCMM analysis, crosstalk, OCV, timing derates, and advanced process nodes.
• 10+ years of experience with timing analysis, cell characterization, and/or SPICE simulation tools, plus strong Python, Tcl, shell scripting, algorithms, and data-structure skills.
• Experience owning production design automation flows, influencing methodology decisions, mentoring engineers, and supporting semiconductor designs through tape-out or sign-off.
• Ability to lead cross-functional technical initiatives across distributed teams and collaborate with EDA vendors.

Nice to have

• Experience with Liberty model generation, LVF, POCV, statistical timing, transistor-level timing, custom IP timing, or FPGA timing deliverables.
• Experience with timing reliability, aging, derating, electromigration, signal integrity, crosstalk, multi-voltage designs, or low-power methodologies.
• Experience applying AI/ML to design automation, including runtime prediction, corner reduction, timing optimization, knowledge capture, or automated debug.
• Master’s or Ph.D. degree in a related technical field.

Culture & Benefits

• Direct technical ownership with substantial architectural latitude and greenfield modernization work.
• Collaboration with specialists in circuit simulation, cell characterization, Liberty generation, FPGA timing models, derating, and reliability methodology.
• Opportunity to influence EDA vendor roadmaps and the company’s future investment in timing methodology.
• Artificial intelligence is used to screen, assess, or select applicants.
• Applicants must be eligible for any required U.S. export authorizations.