PDK LVS Development Engineer (Semiconductor)

TL;DR

PDK LVS Development Engineer (Semiconductor): Developing PDK physical verification runsets (DRC/LVS/PERC) to enable semiconductor design and verification in the Angstrom era. Focus on optimizing LVS-Parasitic Extraction flows, root cause analysis of design issues, and enhancing tool efficiency for hirify.global Foundry.

Location: Hybrid (Penang, Malaysia)

Company

hirify.global Foundry focuses on state-of-the-art semiconductor manufacturing, providing cutting-edge silicon process and packaging technology for the AI era.

What you will do

• Develop PDK physical verification runsets (DRC/LVS/PERC) using Calibre, ICV, or Pegasus.
• Ensure the seamless operability of the LVS-Parasitic Extraction flow.
• Collaborate with technology specification owners, validation teams, and EDA vendors.
• Develop and implement QA and regression solutions to qualify PDK collaterals.
• Conduct root cause analyses for design issues related to process technology.
• Mentor junior team members to develop overall team competency.

Requirements

• Bachelor's degree in Electronics, Electrical, or Computer Engineering (6+ years exp), Master's (4+ years), or PhD (2+ years).
• Expertise in DRC and LVS development using ICV-PXL, Calibre-SVRF, or Pegasus.
• Expertise in PERC verification development.
• Proficiency in scripting languages such as Perl, Python, or TCL.
• Experience with EDA tools like Virtuoso or Custom Compiler.
• Must be based in or able to work in Penang, Malaysia.

Culture & Benefits

• Hybrid work model allowing employees to split time between on-site and off-site work.
• Opportunity to work at the forefront of semiconductor innovation in the AI era.
• Commitment to ethical hiring practices and RBA compliance.
• Integration into a worldwide factory network.