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Product Development Engineer - Scan Diagnostics (Semiconductors)

141 910 - 269 100$
Формат работы
hybrid
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

Product Development Engineer - Scan Diagnostics (Semiconductors): Developing and supporting scan/chain diagnosis infrastructure for high-volume manufacturing of integrated circuits with an accent on fault identification and yield improvement. Focus on optimizing DFT tools, methods, and flows to ensure seamless production ramp-up and high product quality.

Location: Hybrid (US: Santa Clara, CA; Phoenix, AZ; Hillsboro, OR)

Salary: $141,910.00 - $269,100.00 USD

Company

hirify.global is a global leader in semiconductor innovation and manufacturing, focused on delivering world-class integrated circuit solutions.

What you will do

  • Create and support Scan/Chain Diagnosis infrastructure and processes for HVM products.
  • Perform fail-based and volume diagnostic analysis to drive continuous yield improvement.
  • Develop and optimize tools, methods, and flows for Design for Test (DFT) and yield analysis.
  • Collaborate with internal teams and EDA vendors to implement the latest diagnostic methodologies.
  • Define and monitor DFX quality metrics, including coverage, test cost, and debuggability.
  • Work with Design and New Product Introduction (NPI) teams to ensure diagnostic readiness.

Requirements

  • Bachelor's degree in engineering or a related field (Master's or Ph.D. preferred).
  • 4+ years of experience in DFT, Scan Diagnostics, Post-Si diagnostics, or Yield Analysis.
  • Proficiency in Python, TCL, C-Shell, or PERL scripting.
  • Must be based in or able to work from assigned hirify.global sites in the USA.
  • Strong communication and teamwork skills.

Nice to have

  • Experience with Siemens Tessent Test and Yield Analysis tools.
  • Experience with Synopsys Yield Explorer.
  • Knowledge of SOC/IP DFT control architecture (e.g., JTAG, IJTAG, IEEE1500).
  • Experience in Custom and/or ASIC circuit design.

Culture & Benefits

  • Hybrid work model allowing split time between on-site and off-site work.
  • Competitive total compensation package including stock bonuses.
  • Comprehensive health, retirement, and vacation benefit programs.
  • Exposure to the entire semiconductor product lifecycle, from initial definition to HVM.

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