7 дней назад
Senior Design Verification Engineer (Wireless PHY/MAC)
124 600 - 231 400$
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Описание вакансии
Текст:
TL;DR
Senior Design Verification Engineer (Wireless PHY/MAC): Developing verification strategies, test environments, and coverage plans for digital modem designs powering low-power wireless products with an accent on SystemVerilog/UVM, functional debugging, and wireless PHY/MAC verification. Focus on closing functional and code coverage, correlating pre-silicon and post-silicon results, and supporting silicon bring-up across complex connected-device systems.
Location: Austin, Texas, United States
Annual base pay: $124,600–$231,400 USD
Company
develops low-power wireless connectivity and embedded technology for smart home, industrial IoT, and smart city applications.
What you will do
- Define and execute verification strategies for digital modem designs across key wireless use cases.
- Develop scalable verification environments, test benches, and stimuli using SystemVerilog, UVM, or similar methodologies.
- Drive functional and code coverage toward complete verification closure.
- Debug design issues and identify root causes in collaboration with design, architecture, firmware, validation, and system teams.
- Support silicon bring-up and correlate pre-silicon verification results with post-silicon behavior.
- Improve verification methodologies, tools, and automation workflows.
Requirements
- BSEE, computer engineering, or a related degree.
- 3–6 years of experience in digital design verification, preferably focused on modem or wireless PHY designs.
- Experience with SystemVerilog and UVM or comparable verification methodologies.
- Strong digital design fundamentals, verification knowledge, debugging skills, and problem-solving ability.
- Experience with Python or Perl scripting for automation.
- Basic understanding of wireless communication systems or digital signal processing, plus the ability to work collaboratively across teams.
Nice to have
- Experience verifying BLE, Wi-Fi, Zigbee, or similar wireless standards.
- Knowledge of constrained-random and coverage-driven verification or SystemVerilog assertions.
- Experience with C/C++, MATLAB, mixed-signal or system-level verification, and analog/RF co-simulation.
- Exposure to post-silicon validation, lab bring-up, low-power verification, or power-aware methodologies.
Culture & Benefits
- Medical, dental, and vision plans, including PPO and HSA options.
- Flexible vacation plan, life and disability coverage, and flexible spending accounts.
- 401(k) plan with company match and Roth option.
- Equity rewards, annual cash bonus eligibility, and competitive total compensation.
- Tuition reimbursement, adoption assistance, backup childcare, commuter and legal benefits, and pet insurance.
- Paid volunteer days, charitable contribution matching, and monthly wellness offerings.
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