Senior Staff Design Verification Engineer (Semiconductor)

TL;DR

Senior Staff Design Verification Engineer (Semiconductor): Developing and executing simulation test benches in UVM to verify SoC circuitry for AI, cloud, and telecom applications with an accent on correctness and performance. Focus on root-causing simulation failures, ensuring coverage closure, and mentoring junior engineers to achieve project goals.

Location: Santa Clara, CA

Salary: $134,390 - $201,300 per annum

Company

hirify.global provides semiconductor solutions that serve as essential building blocks for data infrastructure across enterprise, cloud, AI, and carrier architectures.

What you will do

• Implement simulation test benches using UVM.
• Develop and execute test plans to verify the correctness and performance of the design.
• Own and debug simulation failures to identify root causes of problems.
• Collaborate with logic designers on test plan development, debug, coverage closure, and gate-level simulations.
• Coach and mentor junior engineers to ensure successful project outcomes.

Requirements

• Bachelor's degree in CS, Electrical Engineering or related fields with 7+ years of experience, or a Master's degree with 5+ years of experience.
• Strong background in SoC verification and test bench development using UVM, System Verilog, C++, and DPI.
• Deep understanding of OOP, white-box/black-box testing, directed/random testing, and gate-level simulations.
• Must be eligible to access export-controlled information as defined under U.S. law.
• Effective interpersonal and teamwork skills.

Culture & Benefits

• Financial well-being programs, including an employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental and physical health resources.
• Recognition and service awards to celebrate contributions and milestones.