Senior Design Verification Engineer (ASIC)

TL;DR

Senior Design Verification Engineer (ASIC/UVM): Verifying memory controllers and top-level SoC designs for breakthrough post-silicon computing technology with an accent on HBM interfaces, fabrics, and custom compute cores. Focus on building UVM-based testbenches, developing comprehensive coverage models, and ensuring functional correctness of high-bandwidth, low-latency compute workloads.

Location: Remote in the USA or onsite in Santa Clara, CA; New York City, NY; or San Francisco, CA

Salary: $250,000–$300,000

Company

hirify.global is recruiting for a well-funded start-up developing fundamentally new technology to extend Moore's Law beyond the limits of silicon.

What you will do

• Define and develop verification plans for top-level systems including HBM interfaces, fabrics, and memory controllers.
• Build and maintain UVM-based testbenches to simulate complex SoC/ASIC designs.
• Develop stimulus, checkers, monitors, and coverage models for comprehensive verification.
• Debug RTL and testbench issues using waveform analysis and simulations.
• Collaborate with RTL designers, architects, and firmware teams to ensure end-to-end functional correctness.
• Mentor junior engineers and drive improvements in verification methodologies and flows.

Requirements

• Must be based in the USA.
• B.S./M.S. in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in ASIC/SoC design verification.
• Strong hands-on experience with UVM and SystemVerilog.
• Solid understanding of DRAM, HBM2/2E/3, and NOC/Fabric protocols.
• Experience verifying at the top level, not just block level.

Nice to have

• Experience with custom compute cores (RISC-V, AI/ML accelerators, DSPs).
• Familiarity with simulation tools like VCS, Questa, or XSIM.
• Leadership or 3rd party vendor management experience.