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Senior Staff Engineer, ASIC/VLSI Synthesis and Design (ASIC)

135Β 900 - 201Β 130$
Π€ΠΎΡ€ΠΌΠ°Ρ‚ Ρ€Π°Π±ΠΎΡ‚Ρ‹
onsite
Π’ΠΈΠΏ Ρ€Π°Π±ΠΎΡ‚Ρ‹
fulltime
Π“Ρ€Π΅ΠΉΠ΄
senior
Английский
b2
Π‘Ρ‚Ρ€Π°Π½Π°
US
Вакансия ΠΈΠ· списка Hirify.GlobalВакансия ΠΈΠ· Hirify Global, списка ΠΌΠ΅ΠΆΠ΄ΡƒΠ½Π°Ρ€ΠΎΠ΄Π½Ρ‹Ρ… tech-ΠΊΠΎΠΌΠΏΠ°Π½ΠΈΠΉ
Для мэтча ΠΈ ΠΎΡ‚ΠΊΠ»ΠΈΠΊΠ° Π½ΡƒΠΆΠ΅Π½ Plus

ΠœΡΡ‚Ρ‡ & Π‘ΠΎΠΏΡ€ΠΎΠ²ΠΎΠ΄

Для мэтча с этой вакансиСй Π½ΡƒΠΆΠ΅Π½ Plus

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TL;DR

Senior Staff Engineer (ASIC/VLSI Synthesis): Developing and validating timing constraints and front-end implementation flows for high-performance SoC designs with an accent on logic synthesis and timing closure. Focus on optimizing interconnect bandwidth and memory capacity for Generative AI infrastructure using advanced technology nodes like 5nm and 4nm.

Location: Irvine, CA

Salary: $135,900 – $201,130 per annum

Company

hirify.global provides semiconductor solutions and innovative technology enabling data infrastructure across enterprise, cloud, and AI architectures.

What you will do

  • Develop and validate timing constraints for complex SoC designs.
  • Collaborate with Architecture, RTL, DFT, and Analog teams to define timing modes and constraints for synthesis, PnR, and sign-off flows.
  • Own front-end implementation tasks including synthesis, UPF development, and Logical Equivalence Checks (LEC).
  • Perform Physical Aware Synthesis using industry-standard tools such as Fusion Compiler.
  • Automate front-end flows and processes using Tcl or Python scripting.
  • Ensure compliance with netlist handoff criteria and document best practices for continuous project improvement.

Requirements

  • Bachelor's degree in CS, Electrical Engineering, or related field with 5-10 years of experience (or Master's/PhD with 3-5 years).
  • Minimum 5 years of industry experience in ASIC implementation and synthesis.
  • Strong understanding of ASIC design flows from RTL to GDSII and STA methodologies.
  • Proficiency with synthesis tools, STA tools, and scripting languages (Tcl, Perl).
  • Experience with high-complexity silicon in advanced technology nodes, preferably TSMC N4/N5.
  • Must be eligible to access export-controlled information as defined under U.S. law.

Nice to have

  • Experience with UPF validation using tools like Conformal Low Power (CLP).
  • Experience performing functional ECOs using Conformal ECO.
  • Proven track record of meeting performance, power, and area goals in successful designs.

Culture & Benefits

  • Employee stock purchase plan with a 2-year look back.
  • Comprehensive family support programs to balance work and home life.
  • Robust mental and physical health resources.
  • Recognition and service awards to celebrate professional milestones.

Π‘ΡƒΠ΄ΡŒΡ‚Π΅ остороТны: Ссли Ρ€Π°Π±ΠΎΡ‚ΠΎΠ΄Π°Ρ‚Π΅Π»ΡŒ просит Π²ΠΎΠΉΡ‚ΠΈ Π² ΠΈΡ… систСму, ΠΈΡΠΏΠΎΠ»ΡŒΠ·ΡƒΡ iCloud/Google, ΠΏΡ€ΠΈΡΠ»Π°Ρ‚ΡŒ ΠΊΠΎΠ΄/ΠΏΠ°Ρ€ΠΎΠ»ΡŒ, Π·Π°ΠΏΡƒΡΡ‚ΠΈΡ‚ΡŒ ΠΊΠΎΠ΄/ПО, Π½Π΅ Π΄Π΅Π»Π°ΠΉΡ‚Π΅ этого - это мошСнники. ΠžΠ±ΡΠ·Π°Ρ‚Π΅Π»ΡŒΠ½ΠΎ ΠΆΠΌΠΈΡ‚Π΅ "ΠŸΠΎΠΆΠ°Π»ΠΎΠ²Π°Ρ‚ΡŒΡΡ" ΠΈΠ»ΠΈ ΠΏΠΈΡˆΠΈΡ‚Π΅ Π² ΠΏΠΎΠ΄Π΄Π΅Ρ€ΠΆΠΊΡƒ. ΠŸΠΎΠ΄Ρ€ΠΎΠ±Π½Π΅Π΅ Π² Π³Π°ΠΉΠ΄Π΅ β†’