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2 дня назад

Staff Design Verification Engineer (Mixed-Signal ASIC)

Формат работы
hybrid
Тип работы
fulltime
Грейд
lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Staff Design Verification Engineer (SystemVerilog/UVM): Developing and executing end-to-end functional verification for mixed-signal IC solutions with an accent on UVM-based testbenches and block/chip-level verification. Focus on implementing constrained-random test suites, performing coverage closure, and debugging complex timing-related issues in ASICs.

Location: Hybrid (Austin, TX / Chandler, AZ / Greensboro, NC). Candidates must be able to access technical data without a requirement for an export license.

Company

hirify.global is a leader in mixed-signal processing, providing innovative end-user solutions for the world's top consumer brands.

What you will do

  • Develop comprehensive verification plans aligned with design and system requirements for mixed-signal ASICs.
  • Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions.
  • Create directed and constrained-random test suites to ensure robust functional coverage.
  • Implement and drive functional and code coverage closure.
  • Conduct failure analysis, regression triage, and debug functional and timing-related issues.
  • Collaborate cross-functionally with digital/analog design, firmware/software, and manufacturing test teams.

Requirements

  • Degree in Electrical Engineering, Computer Engineering, or a related field (BS + 7 years, MS + 5 years, or PhD + 3 years of experience).
  • Strong proficiency with HDLs (Verilog/VHDL) and HVLs (SystemVerilog with UVM).
  • Significant industry experience in silicon design and/or ASIC verification.
  • Solid understanding of digital design principles and system architecture.
  • Ability to access technical data without an export license.

Nice to have

  • Experience verifying mixed-signal ASICs in complex SoC environments.
  • Knowledge of signal processing concepts relevant to mixed-signal designs.
  • Experience with SystemVerilog Assertions (SVA), formal verification, or hardware emulation/acceleration.

Culture & Benefits

  • Award-winning culture based on inclusion, fairness, and meaningful community engagement.
  • Highly collaborative and technically rigorous work environment.
  • Focus on delivering enjoyable employee experiences and career growth.

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