Principal ASIC Verification Engineer

TL;DR

Principal ASIC Verification Engineer (AI/HPC Networking): Define verification strategy and develop UVM testbenches for complex SoCs in high-performance computing and AI interconnects with an accent on Ethernet protocols, RDMA/RoCE, and coverage closure. Focus on driving first-pass silicon success, collaborating with design and emulation teams, and utilizing AI tools for productivity.

Location: Remote for employees residing within the United States

Company

hirify.global delivers high-performance networking solutions for AI and HPC datacenters, integrating hardware, software, and systems for GPU/CPU clusters.

What you will do

• Define SOC-level verification strategy, technical planning, and direction.
• Drive UVM environment development to verify RTL at block, unit, and SOC levels.
• Develop and execute functional tests, instrument testbenches for coverage, and close coverage metrics.
• Collaborate with design, software, emulation, and silicon validation teams for design quality.
• Guide team on AI tools, enforce coding/verification guidelines, and mentor members.

Requirements

• Reside within the United States for remote position.
• 15+ years experience with UVM/SystemVerilog, complex SOC verification (multi-clock/reset domains).
• Hands-on with VCS simulation, Verdi debugging, ground-up testbench development, Git/SVN.
• B.S. in Computer Engineering, Computer Science, or Electrical Engineering.

Nice to have

• M.S. in relevant field.
• 15+ years in networking hardware verification (50G/100G/400G Ethernet, TCP/IP, RDMA/RoCE, IPSec).
• Scripting (TCL, Python, Perl, Shell).
• Track record of first-pass ASIC/system success.

Culture & Benefits

• Competitive pay with equity, incentives, medical/dental/vision, disability/life insurance.
• 401(k) with company match, Open Time Off, sick time, bonding/pregnancy leave.
• Flexible work environment, global team across U.S. states and countries.
• Collaborate with semiconductor industry leaders on cutting-edge AI/HPC tech.