Senior Design Verification Engineer (Mixed-Signal ASIC)

TL;DR

Senior Design Verification Engineer (Mixed-Signal ASIC): Developing and implementing functional verification for mixed-signal IC solutions with an accent on UVM-based testbenches and end-to-end verification across block and chip levels. Focus on creating constrained-random test suites, performing failure analysis, and ensuring robust functional coverage closure.

Location: Hybrid (Austin, TX / Chandler, AZ / Greensboro, NC)

Company

A leading mixed-signal processing company providing innovative high-quality IC solutions for the world's top consumer brands.

What you will do

• Develop comprehensive verification plans and perform functional verification of custom mixed-signal ASICs at block and chip level.
• Design and implement UVM-based testbenches, including infrastructure, scoreboards, checkers, and assertions.
• Create directed and constrained-random test suites to ensure robust functional coverage.
• Implement and drive functional and code coverage closure, conducting failure analysis and regression triage.
• Run and debug gate-level simulations and develop digital and mixed-signal behavioral models.
• Collaborate cross-functionally with analog/digital design, systems, firmware, and manufacturing test teams.

Requirements

• Degree in Electrical Engineering, Computer Engineering, or a related field.
• Bachelor’s with 5+ years, Master’s with 3+ years, or PhD of relevant industry experience in silicon design/ASIC verification.
• Strong proficiency in HDLs (Verilog/VHDL) and HVLs (SystemVerilog with UVM/OVM/AVM).
• Solid understanding of digital design principles and system architecture.
• Experience with testbench architecture, stimulus generation, and coverage analysis.
• Must be able to access technical data without a requirement for an export license.

Nice to have

• Experience verifying mixed-signal ASICs in complex SoC environments.
• Knowledge of signal processing concepts relevant to mixed-signal designs.
• Experience with SystemVerilog Assertions (SVA).
• Exposure to formal verification, hardware emulation, or software-driven verification.

Culture & Benefits

• Award-winning culture founded on inclusion, fairness, and meaningful community engagement.
• Collaborative and technically rigorous work environment.
• Focus on providing enjoyable employee experiences and professional growth.
• Hybrid work model offering a balance of office and remote presence.