Principal Microarchitect (AI)

TL;DR

Principal Microarchitect (AI): Designing execution pipelines and control logic for next-generation AI infrastructure with an accent on performance-per-watt and chip-level innovation. Focus on optimizing datapaths, memory hierarchies, and implementing modern numeric formats to enable large-scale model inference.

Location: Must be based in Santa Clara, New York City, or San Francisco

Salary: $250,000–$325,000

Company

Early-stage startup backed by Tier-1 VC rethinking AI infrastructure from first principles to deliver superior performance-per-watt for inference.

What you will do

• Design execution pipelines, scheduling, and control logic for AI accelerators.
• Define datapaths, register files, scratchpads, and local memory hierarchies.
• Implement support for modern numeric formats including FP16, BF16, FP8, and FP4.
• Optimize for performance, utilization, power, and area while balancing compute throughput with memory bandwidth.
• Collaborate with architecture, compiler, kernel, and performance teams to analyze AI workloads.
• Lead and support RTL implementation, verification, timing closure, and post-silicon performance tuning.

Requirements

• Strong background in AI compute or accelerator design with experience designing complex units across multiple process generations.
• Deep understanding of matrix and vector pipelines, floating point numerics, and quantization.
• Proven experience delivering real silicon.
• MS or PhD and 3-5 years of experience, or equivalent.
• Must be located in Santa Clara, CA; New York City, NY; or San Francisco, CA.

Nice to have

• Experience in startup or early-stage silicon programs.

Culture & Benefits

• Opportunity for massive ownership and high impact in a ground-up build.
• Collaborative environment with industry veterans and Tier-1 VC backing.
• Focus on solving fundamental economic shifts in large-scale model inference.