AI Subsystems Physical Design Lead (AI)

TL;DR

AI Subsystems Physical Design Lead (ASIC/AI): Owning timing for subsystems in an AI accelerator chip with an accent on synthesis, place and route, and timing closure. Focus on optimizing PPA, collaborating with RTL designers to assess buildability, and implementing high-performance CPUs on advanced process nodes.

Location: Hybrid; Must be based in Austin, TX, Fort Collins, CO, or Santa Clara, CA

Salary: $100k - $500k

Company

hirify.global is leading the industry on cutting-edge AI technology, developing high-performance RISC-V CPUs and AI platforms.

What you will do

• Own timing for subsystems in an AI accelerator chip.
• Collaborate with RTL designers to assess the buildability and PPA of micro-architectural features.
• Develop timing constraints and drive the transition to physical design implementation.
• Execute synthesis, place and route, timing analysis, and closure.
• Optimize power and select micro-architecture design points to meet die-size and PPA goals.

Requirements

• BS/MS/PhD in EE/ECE/CE/CS.
• Proven experience in synthesis, PnR, and timing closure on taped-out designs.
• Expertise with Innovus, PrimeTime, RedHawk, and scripting languages (Tcl, Perl, Python).
• Deep understanding of advanced node challenges and low-power design techniques.
• Must be eligible to access U.S. export-controlled technology (subject to EAR regulations).

Culture & Benefits

• Opportunity to implement cutting-edge AI accelerators and CPUs on the most advanced process nodes.
• Work with innovative PPA optimization techniques and next-generation chiplet architectures.
• End-to-end ownership from flow development to signoff.
• Competitive compensation package and benefits.