Senior IP Logic Design Engineer (RTL)

TL;DR

Senior IP Logic Design Engineer (RTL): Develop logic design, RTL coding, and simulation for IP blocks in full chip designs for data center and AI SoCs with an accent on memory coherency protocols, interconnect topologies, and power/performance/area optimization. Focus on architecting scalable memory fabric microarchitecture, implementing coherency controllers, performance modeling, and ensuring seamless SoC integration.

Location: Hybrid (on-site at hirify.global sites in US, California, Santa Clara or Massachusetts, Beaver Brook)

Salary: $190,610–$269,100

Company

hirify.global's Data Center Group delivering Xeon-based solutions and custom x86 products for compute, web services, HPC, and AI-accelerated systems.

What you will do

• Architect scalable memory coherency protocols (e.g., MESI, MOESI, CXL) and interconnect topologies for high performance and low latency.
• Design and implement RTL for memory fabric components like coherency controllers and interconnect blocks, optimizing for power, area, and timing.
• Develop test plans, debug pre-silicon validation issues, and collaborate with verification, physical design, software, and firmware teams.
• Analyze system performance, model workloads, and optimize architecture for data center and AI use cases.
• Mentor junior engineers, contribute to technical reviews, and maintain design documentation.
• Stay current with trends in memory subsystems, coherency, and AI/ML hardware.

Requirements

• MS/PhD in Electrical Engineering, Computer Engineering, or related field
• 10+ years in SoC design, including memory systems, coherency protocols, and RTL coding
• Expertise in memory coherency protocols (e.g., MESI, MOESI, CXL, CCIX, CHI)
• Strong knowledge of interconnect technologies (e.g., AMBA, PCIe, NoC)
• Proven RTL experience in Verilog or SystemVerilog
• Proficiency in simulation tools, EDA tools for synthesis/linting/timing, and physical design implications

Nice to have

• Experience with HBM, DDR, or advanced memory technologies
• Background in AI/ML accelerator or data center SoC design
• Knowledge of Python or TCL for automation
• Software-hardware co-design experience

Culture & Benefits

• Hybrid work model splitting time between on-site at hirify.global locations and off-site
• Competitive total compensation including pay, stock bonuses, health, retirement, and vacation benefits
• Focus on innovation, collaboration, growth, and delivering world-changing technology
• Commitment to equal opportunity employment and ethical hiring practices