Fellow, High-Speed IO Design (AI)

TL;DR

Fellow, High-Speed IO Design (AI): Define the long-term vision for differentiated die-to-die chiplet PHY IP and key AMS blocks in advanced deep sub-micron FinFET technologies with an accent on high-speed SerDes/datacomm and strategic technical direction. Focus on architecting next-generation solutions, solving novel technical challenges, and ensuring scalability and reusability across the product portfolio.

Location: Hybrid, based out of Fort Collins, Colorado, United States. Employment contingent upon eligibility to access U.S. export-controlled technology (may require U.S. citizenship/permanent residency or license approval).

Compensation: $100k–$500k (base + variable).

Company

AI technology leader developing high-performance RISC-V CPUs and platforms unifying software, compilers, networking, and semiconductors.

What you will do

• Establish technical roadmap for die-to-die chiplet PHY IP in advanced FinFET nodes.
• Drive strategic solutions for emerging technical problems using novel techniques.
• Mentor and advise engineering teams to foster innovation and excellence.
• Own company-level outcomes for high-performing, scalable AMS IP across products.

Requirements

• BSEE/MSEE/PhD with extensive experience in analog/mixed-signal IC design, PLL/AMS in FinFET processes.
• Proven track record driving functional goals with company-wide impact.
• Deep expertise in high-speed datacomm/SerDes and die-to-die PHY design.
• Mastery of full silicon lifecycle and complex circuits (bias generators, LDOs, ADCs/DACs).
• Eligible for U.S. export-controlled technology access.

Culture & Benefits

• Collaborative environment valuing curiosity, innovation, and solving hard problems.
• Highly competitive compensation package and benefits.
• Equal opportunity employer.