Staff Design Verification Engineer (AI)

TL;DR

Staff Design Verification Engineer (AI): Creating best-in-class silicon for high-performance and sustainable Generative AI with an accent on verification methodology and system-level validation. Focus on developing hybrid SoC testbenches, implementing simulation acceleration techniques, and ensuring verification closure for silicon milestones.

Location: Hybrid based in the San Francisco Bay Area

Salary: $200,000–$300,000

Company

A high-performing semiconductor company founded by industry veterans pushing the boundaries of LLMs through advanced silicon design.

What you will do

• Contribute to verification methodology across blocks, subsystems, and full-chip levels.
• Own verification execution for subsystems and chips, ensuring closure for silicon milestones.
• Develop and maintain hybrid SoC testbenches.
• Design and implement advanced simulation acceleration techniques.
• Build reusable and scalable verification components across simulation, emulation, and post-silicon platforms.
• Collaborate with cross-functional teams to validate system-level performance.

Requirements

• Expertise in UVM and hybrid SoC testbench development.
• Experience integrating cycle-accurate models.
• Proven record of designing simulation acceleration techniques.
• Ability to create scalable verification components across multiple platforms.
• Experience working with cross-functional teams at the system level.
• Must be based in the San Francisco Bay Area for hybrid work.

Nice to have

• Familiarity with emulation and prototyping platforms and methodologies.
• Hands-on experience with silicon debugging and bring-up.
• Knowledge of Rust.
• Interest in working with AI tools.