Senior Physical Design Engineer (AI)

TL;DR

Senior Physical Design Engineer (AI): Developing next-generation silicon for high-performance generative AI systems with an accent on the full physical design flow from RTL to tapeout. Focus on optimizing PPA, managing complex floorplanning, and ensuring timing and power sign-off for advanced compute architectures.

Location: Mountain View, CA; New York City, NY; San Francisco, CA

Salary: $120,000–$400,000

Company

An early-stage AI hardware startup developing high-performance silicon to power efficient generative AI systems at leading-edge process nodes.

What you will do

• Own physical design execution from RTL to GDSII for subsystems and full-chip deliverables.
• Perform partitioning, floorplanning, synthesis, place & route, and clocking.
• Manage timing, power, EMIR, and physical verification sign-off.
• Drive design reviews and track progress toward key milestones, including design freeze and tapeout.
• Collaborate with Design, Verification, and DFT teams to optimize PPA.
• Support scalable and repeatable implementation strategies across complex silicon programs.

Requirements

• Bachelor’s degree in Electrical Engineering or equivalent.
• 8+ years of experience in ASIC Physical Design.
• Proven track record of owning physical design from early RTL through production silicon.
• Strong understanding of full physical design flow and sign-off methodologies.
• Proficiency in scripting and automation (e.g., Python, TCL, Perl).
• Experience working cross-functionally with Design, Verification, and DFT teams.

Nice to have

• Experience with advanced process nodes and high-performance designs.
• Background in AI, HPC, or other compute-intensive silicon domains.
• Experience working with or managing third-party design services partners.