Advanced ASIC RTL To Netlist Physical Design Lead (ASIC)

TL;DR

Advanced ASIC RTL To Netlist Physical Design Lead (ASIC): Leading the RTL-to-GDSII execution for complex, large-scale mixed-signal ASICs used in next-generation SoC and memory test platforms with an accent on physical design architecture, timing closure, and advanced process nodes. Focus on owning chip floorplans, integrating high-speed IPs like PCIe and DDR5/DDR6, and ensuring robust signoff closure.

Location: North Reading, MA, US

Salary: $192,300 – $307,600

Company

hirify.global is a global specialist in test and automation solutions for the semiconductor and electronics manufacturing industries.

What you will do

• Lead and mentor a team of physical design engineers throughout the full project lifecycle.
• Define PD architecture and develop chip floorplans, timing budgets, and power estimates.
• Drive RTL-to-netlist activities including synthesis, LEC, CDC, and static timing analysis (STA).
• Integrate complex high-speed IPs such as PCIe, DDR5/DDR6, UFS, and SerDes.
• Ensure robust signoff closure including DRC/LVS and EM/IR analysis.
• Develop and maintain physical design tool flows and automation.

Requirements

• 10+ years of hands-on ASIC physical design experience, including leadership of complex PD projects.
• Proven experience at advanced technology nodes (16nm and below).
• Deep expertise in RTL-to-GDSII flows, timing closure, and signoff methodologies.
• Proficiency with industry-standard EDA tools, specifically Cadence.
• Strong scripting skills using Tcl, Python, and/or Make.
• BS or MS in Electrical Engineering.

Culture & Benefits

• Comprehensive health programs including medical, dental, and vision.
• Retirement savings plans and life/disability insurance.
• Paid vacation, holidays, and tuition assistance programs.
• High technical ownership and visibility within an engineering-driven culture.