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1 день назад

Senior PCIe ASIC Design Engineer (AI)

Формат работы
remote (только USA)
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR

Senior PCIe ASIC Design Engineer (PCIe/ASIC): Leading the design and integration of PCIe controllers into next-generation SoCs with an accent on high-performance interconnect scalability and silicon bring-up. Focus on optimizing the PCIe stack from PHY tuning to DMA efficiency and debugging complex functional issues at RTL and silicon levels.

Location: Remote (Must be based in the United States)

Company

hirify.global delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters.

What you will do

  • Own end-to-end integration of PCIe IP into complex ASIC designs.
  • Collaborate with IP vendors, architecture, verification, and software teams to deliver robust PCIe subsystems.
  • Drive performance optimization across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency.
  • Lead silicon bring-up and validation of PCIe links in the lab, working with board and firmware teams.
  • Debug functional and performance issues at RTL, gate-level, and silicon.
  • Mentor junior engineers and define PCIe subsystem development best practices.

Requirements

  • BS/MS in Electrical Engineering, Computer Engineering, or a related field.
  • 10+ years of industry experience in ASIC/SoC design focusing on PCIe controller integration.
  • Proven experience in silicon bring-up and debug of high-speed interfaces.
  • Deep understanding of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training.
  • Hands-on experience with PCIe verification environments, performance tuning, and power-aware design.
  • Must be based in the United States.

Nice to have

  • Experience with PCIe Gen5/Gen6 and advanced retimer or switch solutions.
  • Exposure to CXL, CCIX, or other cache-coherent interconnects.
  • Background in data center or AI/ML accelerator architectures.
  • Experience with emulation and prototyping platforms (e.g., ZeBu, Palladium, HAPS).

Culture & Benefits

  • Competitive compensation package including equity, cash, and incentives.
  • Comprehensive medical, dental, and vision coverage, plus disability and life insurance.
  • 401(k) with company match.
  • Open Time Off (OTO), generous paid holidays, and sick time.
  • Dynamic, flexible work environment collaborating with semiconductor industry leaders.

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