Senior ASIC Design Engineer (AI/HPC)

TL;DR

Senior ASIC Design Engineer (AI/HPC): Translate system-level requirements into detailed architecture and design specifications, develop complex RTL logic mainly in Verilog or SystemVerilog, handle synthesis, timing closure, and block-level simulation for SoCs. Focus on designing processor sub-systems, AI acceleration cores, networking datapaths, interfacing with verification and hardware teams, and lab bring-up.

Global search, company headquartered in Ottawa, Canada

$140,000 to $190,000 plus company bonus and benefits

Company

Headquartered in Ottawa, Canada, specializing in ASIC and FPGA design, verification, and embedded software development services to augment clients' teams.

What you will do

• Translate system-level requirements into implementable architecture and design specifications.
• Develop synthesis and timing constraints for complex blocks and sub-systems.
• Design and implement RTL logic, run simulations, synthesis, and timing closure.
• Interface with verification, design, hardware, and support teams.
• Perform lab bring-up, product integration, and customer technical support.

Requirements

• Minimum 8 years in ASIC design.
• Experience with RTL design, synthesis, STA, lint, LEC, PnR.
• Developing synthesis/timing constraints for large timing-critical designs.
• Lab environment experience troubleshooting to system level.
• Knowledge in ARM/RISC-V processors, caches, AI cores, networking datapaths, interfaces like Ethernet, PCIe, AXI.
• Test verification and scripting experience.
• Self-starter, team player, leader.

Culture & Benefits

• Challenging technical work with leading technology companies.
• Environment appreciating, trusting, and engaging staff.
• Focus on work-life balance with flexibility for family and life outside work.
• Company bonus and comprehensive benefits plan.