Physical Design Engineer (FPGA)

Location: San Jose, California, United States; onsite, Shift 1

Salary: $105,000–$120,000 USD annually for the Bay Area California region, plus incentive opportunities.

Company

hirify.global is a pure-play FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

• Support block-level and top-level physical design implementation for FPGA and ASIC-style designs, including floorplanning, placement, clock tree synthesis, routing, and physical verification.
• Optimize designs for timing, power, area, congestion, routability, and manufacturability with senior physical design engineers.
• Participate in netlist handoff, constraints setup, synthesis and physical-design handoff, timing closure, ECO implementation, and signoff readiness.
• Analyze timing, power, congestion, design-rule, setup/hold, clocking, IR-drop, and other physical-design issues.
• Collaborate with RTL, DFT, CAD, verification, and other cross-functional teams to resolve implementation and flow issues.
• Develop automation scripts and support silicon bring-up and post-silicon debug activities.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field, with 2+ years of industry experience in physical design, ASIC/SoC backend implementation, or related semiconductor engineering.
• Knowledge of floorplanning, placement, CTS, routing, timing closure, static timing analysis, timing constraints, and setup/hold concepts.
• Experience with physical design and signoff tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, Fusion Compiler, or similar.
• Experience reviewing timing, congestion, area, and power reports, plus familiarity with DRC/LVS and physical signoff checks.
• Scripting or automation experience with Tcl, Python, Perl, or similar languages, along with knowledge of RTL-to-signoff semiconductor flows and CMOS/VLSI concepts.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with advanced-node physical design, low-power implementation, FPGA, SoC, or high-performance semiconductor products.
• Familiarity with power planning, IR-drop, signal integrity, electromigration, physical signoff, and Linux/Unix environments.
• Strong problem-solving skills and collaborative team experience.

Culture & Benefits

• Collaborative work across architecture, RTL, DFT, timing, power, verification, CAD, and silicon engineering teams.
• Opportunity to develop technical depth in physical design and backend implementation.
• Incentive opportunities based on individual and company performance.
• Regular employment position based in the Bay Area.