Physical Design Implementation and Signoff Methodology Lead & Architect (AI/ML)

Location: San Jose, California, United States; Shift 1, United States of America.

Salary: $231,500–$341,075 USD annually for the Bay Area, with incentive opportunities.

Company

hirify.global develops programmable logic and adaptive computing solutions for data centers, networking, automotive, aerospace, and industrial applications.

What you will do

• Own the end-to-end physical design implementation and signoff methodology across the product portfolio.
• Define scalable flows and standards for place-and-route, EMIR analysis, timing signoff, and power signoff.
• Introduce AI/ML-driven prediction, automated debug, fix recommendations, and intelligent flow orchestration.
• Establish golden reference flows, signoff criteria, and quality gates supporting reliable first-pass tapeouts.
• Qualify next-generation methodologies with process technology teams, EDA vendors, and design teams.
• Lead root-cause analysis, tapeout readiness reviews, cross-functional design reviews, and technical mentorship.

Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 12+ years of physical design experience for Principal Engineer or 15+ years for Senior Principal Engineer, including at least 8 years developing and deploying implementation or signoff methodology.
• Deep expertise in at least two of place-and-route implementation, EMIR analysis, and timing/power signoff, with working knowledge of the third domain.
• Experience deploying physical design methodologies across multiple tapeouts and process technology nodes.
• Hands-on proficiency with industry-standard EDA tools such as RedHawk-SC, PrimeTime, PrimePower, Fusion Compiler, Innovus, Voltus, or Tempus.
• Working knowledge of AI/ML for physical design, Python and Tcl automation, advanced-node challenges, parasitic extraction, and reliability signoff.

Nice to have

• Production deployment of AI/ML-based EDA solutions, including prediction, ECO generation, or anomaly detection.
• Methodology strategy experience at Principal or Senior Principal Engineer level across multiple product generations.
• Foundry PDK and leading-edge process-node qualification experience.
• Patents, publications, or conference contributions in physical design, signoff, or AI/ML for EDA.

Culture & Benefits

• Senior individual-contributor role focused on technical authority, architecture, and influence rather than people management.
• Opportunity to shape methodology across multiple product generations and design teams.
• Collaboration with experienced physical design and CAD engineers.
• Incentive opportunities based on individual and company performance.
• Applicants must be eligible for any required U.S. export authorizations.