Physical Design Lead — Execution (FPGA)

Location: San Jose, California, United States

Salary: $231,500–$341,075 USD annually for the Bay Area, California.

Company

hirify.global develops programmable logic and adaptive computing solutions for data centers, networking infrastructure, automotive, aerospace, and industrial applications.

What you will do

• Drive physical design execution across blocks and full-chip integration from floorplan through tapeout.
• Own execution schedules, quality gates, risk identification, and mitigation plans.
• Coordinate concurrent block teams, resolve dependencies, and support full-chip closure.
• Serve as an escalation point for execution blockers and critical-path recovery.
• Engage senior customer technical stakeholders and represent physical design execution in technical discussions.
• Partner with methodology and CAD teams and mentor physical design engineers.

Requirements

• 12+ years of physical design experience for Principal Engineer or 15+ years for Sr. Principal Engineer, with at least four advanced-node full-chip tapeouts and direct execution ownership.
• Bachelor’s, Master’s, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
• Hands-on expertise in floorplanning, placement, clock-tree synthesis, routing, timing closure, power closure, and signoff.
• Experience with advanced-node physical design and tools such as Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus, Tempus, Voltus, Ansys RedHawk-SC, and Siemens Calibre or equivalents.
• Working knowledge of STA, EMIR, physical verification, formal equivalence, and low-power verification flows.
• Applicants must be eligible for required U.S. export authorizations.

Nice to have

• Experience as a full-chip or major-subsystem implementation lead.
• Customer-facing physical design execution review experience.
• Experience mentoring or informally leading teams without formal management authority.

Culture & Benefits

• Senior individual-contributor role focused on technical leadership rather than people management.
• Growth path toward full-chip implementation ownership and future implementation leadership.
• Opportunity to work on complex silicon designs with experienced physical design engineers.
• Incentive opportunities based on individual and company performance.