Qubit Control Physical Design Engineer (AI)

Location: Hillsboro, Oregon, United States; hybrid work model with regular on-site work at the assigned hirify.global site

Annual salary: $141,910–$269,100 USD

Company

hirify.global's Corporate Technology Office develops foundational technologies, architectures, and methodologies that advance the company's computing product roadmap.

What you will do

• Drive RTL-to-GDS design convergence using synthesis and place-and-route tools against performance, power, and area targets.
• Deliver block-level physical design, including floor planning, bus and pin placement, power and clock distribution, congestion analysis, and timing closure.
• Analyze and resolve timing, EM/IR, LVS, and DRC violations and lead physical design sign-off activities.
• Collaborate with CAD, methodology, custom IP, and cross-functional engineering teams to optimize tools, memory macros, and standard cell libraries.
• Develop physical design methodologies and automate workflows using scripting and AI tools.
• Support chiplet integration, advanced packaging, and production-quality silicon delivery.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 6+ years of physical design experience, or a master's degree with 4+ years of relevant experience.
• Experience with floor planning, timing constraint definition, synthesis, place-and-route, and product KPI delivery.
• Proficiency in Python, Perl, and TCL for design-flow automation and debugging.
• Hands-on experience with functional equivalence verification, RV reports, and engineering change orders.
• Strong understanding of chiplet integration, advanced packaging, and AI-assisted workflow improvement.
• Experience with physical design techniques and methodologies for power-efficient and high-frequency designs.

Nice to have

• Static timing analysis experience across interfaces such as SerDes and UCIe.
• Experience with Cadence Virtuoso or Synopsys Fusion Compiler.
• Knowledge of asynchronous architectures and circuits.
• EDA software development with Java or C++ and experience mentoring junior engineers.

Culture & Benefits

• Work within a cross-disciplinary Corporate Technology Office focused on advanced computing architectures.
• Hybrid work with time split between the assigned hirify.global site and off-site work.
• Competitive compensation with stock bonuses.
• Health, retirement, and vacation benefits.

Hiring process

• Recruiter discussions determine the location-specific compensation range within the published US range.
• Employment details and work model may be updated during the hiring process.