Senior Physical Design Engineer (ASIC)

TL;DR

Senior Physical Design Engineer (ASIC): Implementing backend flows from netlist to GDSII for challenging blocks and sub-systems with an accent on P&R implementation and timing closure. Focus on optimizing power and area, running IR-drop analysis, and ensuring physical verification in single-digit FinFET technology nodes.

Location: Headquartered in Ottawa, Canada; searching globally

Salary: $130,000 to $180,000

Company

hirify.global specializes in ASIC and FPGA design, verification, and embedded software development services to accelerate client designs.

What you will do

• Run P&R implementation flows and analyze results for high-complexity blocks.
• Create adequate floorplans for physical aware synthesis.
• Drive the design to timing closure and perform physical verification.
• Debug issues related to tools, timing constraints, DFT, and general design.
• Collaborate with design teams to optimize RTL for better implementation.
• Implement timing ECOs and optimize power and area using PrimeTime and IR-drop analysis.

Requirements

• 8+ years of relevant experience in the ASIC digital P&R field.
• Recent experience with leading EDA tools (Synopsys/Cadence) and advanced flows.
• Deep understanding of advanced FinFET technology nodes and DRC rules.
• Proven experience with floor-planning and CTS concepts.
• Strong scripting skills for automation and efficiency.
• Knowledge of Synthesis, StarRC, PT DMSA, RedHawk, Calibre, or Formal verification.

Culture & Benefits

• Engagement in challenging, stimulating technical environments with world-leading innovation.
• Company culture based on trust, appreciation, and individual recognition.
• Strong emphasis on work-life balance to allow time for family and personal interests.
• Competitive compensation including a company bonus and benefits plan.