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19 часов назад

Senior ASIC Synthesis and STA Engineer (Hardware)

109 000 - 174 000CAD
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Senior ASIC Synthesis and STA Engineer (Hardware): Executing front end implementation for IP subsystems with an accent on synthesis, static timing analysis, and logical equivalence checking. Focus on developing timing constraints, validating clock domain crossings, and optimizing synthesis and STA workflows.

Location: Ottawa

Salary: $109,000 - $174,000 CAD

Company

hirify.global is a global leader in high-speed connectivity and optical networking technology.

What you will do

  • Execute front end implementation for IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation.
  • Develop and maintain timing constraints to support synthesis and signoff for subsystem integration.
  • Perform logical equivalence verification between RTL and gate level netlists throughout pre and post layout stages.
  • Validate clock domain crossings for top level ASIC integration to ensure functional integrity.
  • Create and optimize scripts, tools, and documentation to improve synthesis and static timing workflows.
  • Collaborate with ASIC integration, IP development, and physical design teams, as well as external EDA partners.

Requirements

  • B.Sc. in Electrical Engineering, Computer Engineering, or a related discipline.
  • Industry experience using synthesis and/or static timing analysis tools within an ASIC development environment.
  • Knowledge of ASIC implementation flows, including synthesis, timing analysis, LEC, and CDC validation.
  • Familiarity with RTL design principles and hardware description languages (HDL).
  • Ability to manage deliverables to project schedules within multi-disciplinary engineering teams.

Nice to have

  • Experience with floorplanning, Design for Testability (DFT), or place and route.
  • Exposure to deep submicron ASIC technologies and advanced timing closure methodologies.
  • Scripting experience in Python, Tcl, or similar languages.
  • Background in DSP-centric or high-speed ASIC development programs.
  • Experience working with external EDA vendors or foundry technology teams.

Culture & Benefits

  • Flexible work environment prioritizing individual growth, well-being, and belonging.
  • Comprehensive health coverage including medical, dental, and vision plans.
  • Retirement savings plans with company matching (DCPP in Canada, 401(K) in USA).
  • Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
  • Paid sick leave, vacation time, and company-paid holidays.

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