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7 часов назад

Senior Staff Physical Design Manager (ASIC)

165 450 - 247 900$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior/lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

Senior Staff Physical Design Manager (ASIC): Leading physical design teams and methodology for next-generation high-performance processor and data center chips with an accent on advanced CMOS process technology. Focus on technical direction, project resource planning, and ensuring successful tape-outs from netlist to GDS.

Location: Must be based in Santa Clara, CA (Onsite)

Salary: $165,450–$247,900 per annum

Company

hirify.global is a leading semiconductor solutions provider enabling the data infrastructure that connects the world across enterprise, cloud, and AI architectures.

What you will do

  • Provide technical direction, coaching, and mentoring to physical design engineers.
  • Plan and designate project resources while monitoring progress for stakeholders.
  • Partner with ASIC design teams to ensure successful project outcomes.
  • Lead physical design and methodology for high-performance processor and data center chips.
  • Manage customer interfaces for ASIC projects when required.
  • Lead recruiting efforts at local universities and hiring of experienced engineers.

Requirements

  • Must be eligible to access export-controlled information under U.S. law.
  • Bachelor’s degree in CS, Electrical Engineering, or related field with 5-10 years of experience (or Master’s/PhD with 3-5 years).
  • Strong background in ASIC or SOC development.
  • Deep knowledge of physical design from netlist handoff to GDS tape-out.
  • Proficiency in floor planning, place and route, clock tree synthesis, timing closure, and physical verification.
  • Excellent written and oral communication skills for effective collaboration.

Nice to have

  • Experience leading projects within semiconductor product development or tape-out cycles.
  • Proven track record of team mentorship for high performance.
  • Experience as a top-level physical design lead, STA chip lead, or chip DFT lead.
  • Project management experience in ASIC or SOC environments.
  • Experience working with distributed teams.

Culture & Benefits

  • Comprehensive financial well-being programs including an employee stock purchase plan.
  • Robust family support and mental health resources.
  • Recognition and service awards to celebrate contributions.
  • Commitment to diversity and equal opportunity employment.

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