Senior CPU Design Verification Engineer (Silicon)

TL;DR

Senior CPU Design Verification Engineer (Silicon): Lead pre-silicon functional verification of complex CPU and SoC logic with an accent on architectural correctness and functional robustness. Focus on developing SystemVerilog/UVM environments, debugging RTL issues, and improving design quality for next-generation Atom cores.

Location: Hybrid (Austin, TX or Phoenix, AZ)

Salary: $122,440 – $232,190 USD

Company

hirify.global is a global leader in silicon innovation, powering technologies from personal computing and AI to cloud-scale data centers.

What you will do

• Lead pre-silicon functional verification of complex CPU and SoC logic to ensure compliance with microarchitectural specifications.
• Develop and execute verification plans, testbenches, and SystemVerilog/UVM environments for coverage closure.
• Analyze system-level simulations to uncover functional, performance, power, and corner-case issues.
• Debug and root-cause complex RTL and integration issues in collaboration with design teams.
• Influence architecture and microarchitecture definitions by providing early verification feedback.
• Maintain and scale verification infrastructure, methodologies, and automation.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field with 4+ years of experience (or Master’s with 2+ years).
• Proficiency in Design Verification methodologies using SystemVerilog, UVM, and industry-standard EDA tools.
• Proven experience in pre-silicon verification of CPU, SoC, or complex IP designs.
• Must be based in the US and able to work in a hybrid model at assigned hirify.global sites (Austin, TX or Phoenix, AZ).

Nice to have

• Strong debugging skills with C/C++ and Linux-based simulation environments.
• Experience with Python or Perl scripting for automation.
• Deep understanding of CPU microarchitecture and computer architecture concepts.
• Experience with system boot flows and low-power feature verification.

Culture & Benefits

• Opportunity to work on silicon shipping at a global scale.
• Ability to influence CPU architecture decisions early in the design cycle.
• Competitive compensation package including stock bonuses.
• Comprehensive health, retirement, and vacation benefits.
• Hybrid work model allowing a split between on-site and off-site work.