Назад
3 дня назад

ASIC Design Verification Engineer (Hardware)

175 000 - 215 000$
Формат работы
hybrid
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR

ASIC Design Verification Engineer (Hardware): Developing and validating high-performance custom silicon for the autonomous driving compute platform with an accent on UVM/SystemVerilog testbenches and scalable verification plans. Focus on driving functional coverage, debugging complex hardware/software interactions, and optimizing silicon performance and latency.

Location: Hybrid, Mountain View, California

Salary: $175,000—$215,000 USD

Company

Waymo is an autonomous driving technology company building the Waymo Driver to improve mobility and safety through fully autonomous ride-hailing services.

What you will do

  • Translate hardware specifications into comprehensive and scalable verification plans.
  • Develop testbenches, reference models, and stimulus to validate mission-critical functionality.
  • Architect verification environments and contribute to shared tools and reusable methodologies.
  • Evaluate, integrate, and verify third-party Verification IP (VIP) to accelerate development.
  • Define and analyze functional and code coverage metrics to ensure design closure.
  • Establish and advocate for verification best practices across the organization.

Requirements

  • 3+ years of experience building and maintaining complex testbenches using UVM/SystemVerilog.
  • Proven track record with constrained-random generation, functional coverage, and SVA.
  • Deep understanding of digital logic and ability to debug intricate HW/SW interactions.
  • Proficiency in Python for developing automation frameworks and regression management.
  • Excellent verbal and written communication skills for cross-functional collaboration.
  • Strong analytical skills for root-causing failures across RTL and environment layers.

Nice to have

  • Experience with post-silicon bring-up and validation.
  • Familiarity with power-aware verification (UPF) or formal verification.
  • Domain expertise in ML accelerators, NoCs, or high-bandwidth memory.
  • Experience with C/C++ for reference model development.
  • Hands-on experience with PCIe Gen 5/6, DDR5, or Ethernet.
  • Interest in leveraging Generative AI and LLMs to accelerate verification workflows.

Culture & Benefits

  • Competitive base salary and discretionary annual bonus program.
  • Equity incentive plan.
  • Generous company benefits program.
  • Hybrid work schedule.

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