Senior ASIC DV Engineer (UVM)

TL;DR

Senior ASIC DV Engineer (UVM/SOC): Architecting block and full-chip verification environments for complex SOCs targeted towards Touch Controllers and Wireless Charging Chips with an accent on HVLs and constrained random techniques. Focus on debugging RTL and Gate simulations, verifying low power silicon using UPF, and developing mixed-signal simulation test plans.

Location: Must be based in San Jose or Irvine, California, USA

Salary: $141,300 - $226,000 per year

Company

hirify.global is a global technology leader that designs, develops and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Architect block and full-chip verification environments using HVLs (UVM) and constrained random techniques.
• Develop test plans and coverage metrics from specifications for SOCs with embedded CPUs and mixed-signal interfaces.
• Debug RTL and Gate simulations in collaboration with design engineers to verify fixes.
• Write diagnostics for ASIC and FPGA prototype validation.
• Replicate silicon bugs in simulation environments and validate software workarounds or hardware fixes.
• Convert verification tests to test patterns to assist Test Engineers with ATE vector bring-up.

Requirements

• Education and Experience: Bachelors with 12+ years, Masters with 10+ years, or PhD with 7+ years of related experience.
• Strong knowledge of mixed-signal simulations including AMS and Spice.
• Experience verifying low power silicon for mobile applications and proficiency with UPF low power verification flow.
• Ability to translate customer requirements into full chip design and architecture verification.
• Location: Based in the USA (CA)

Culture & Benefits

• Comprehensive medical, dental, and vision plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP) and Employee Assistance Program (EAP).
• Paid sick leave, vacation time, and company-paid holidays.
• Equal opportunity employer providing a diverse and inclusive work environment.