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4 часа назад

Senior Design Engineer (AI SoC)

190 610 - 269 100$
Формат работы
hybrid
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify RU Global, списка компаний с восточно-европейскими корнями
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Описание вакансии

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TL;DR

Senior Design Engineer (AI SoC): Developing logic design, RTL coding, and simulation for AI SoC products from edge devices to data center accelerators with an accent on IP block integration and microarchitecture definition. Focus on optimizing power, performance, area, and timing goals while driving silicon bring-up and post-silicon validation.

Location: Hybrid (Must be based in the US: Folsom, Santa Clara, Hillsboro, or Austin)

Salary: $190,610.00 - $269,100.00 USD

Company

Global leader in semiconductor manufacturing, developing cutting-edge processors and AI hardware for diverse applications from edge to data center.

What you will do

  • Define and document micro-architecture for complex SoC IP blocks and implement RTL using Verilog/SystemVerilog.
  • Integrate IP blocks and subsystems into full chip SoC or discrete component designs.
  • Lead evaluation of architectural trade-offs regarding performance targets, power constraints, and system limitations.
  • Develop and maintain timing constraints, ensuring synthesis and timing-clean designs.
  • Collaborate with verification teams to ensure comprehensive coverage and resolve RTL test failures.
  • Drive silicon bring-up and post-silicon validation, including debug and performance analysis.

Requirements

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • 7+ years of experience in RTL design and implementation for ASIC/SoC development.
  • Must be based in the US (Folsom, Santa Clara, Hillsboro, or Austin).

Nice to have

  • Experience with clock domain crossings, power optimization, and timing closure.
  • Knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures.
  • Proficiency in Python and TCL for automation and design flow optimization.
  • Experience with EDA tools such as VCS, Questa, Xcelium, Spyglass, and FPGA tools (Vivado, Quartus II).

Culture & Benefits

  • Total compensation package including competitive pay and stock bonuses.
  • Comprehensive benefit programs covering health, retirement, and vacation.
  • Hybrid work model allowing a split between on-site and off-site work.
  • Opportunities for continuous learning and professional mentorship.

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