Fullchip Floorplan Design Engineer (ASIC)

TL;DR

Fullchip Floorplan Design Engineer (ASIC): Top-down SoC floorplan activities like IP placement, partitioning, PG grid creation, pin-cutting, bump-planning with an accent on estimating die-area and defining optimal physical dimensions including product costs. Focus on driving execution and supervising progress of smaller blocks or sub-systems, influencing physical placement, shape, channel planning, and managing dependencies between domains.

Location: Hybrid work model at US hirify.global sites (primary: Austin TX; additional: Folsom CA, Santa Clara CA, Fort Collins CO, Beaver Brook MA, Hillsboro OR)

Salary: $141,910.00-269,100.00

Company

Global leader in semiconductor innovation for data centers, HPC, AI-accelerated systems, and x86 computing.

What you will do

• Perform top-down SoC floorplan activities including best IP placement for latency/area, partitioning, PG grid, pin-cutting, bump-planning in collaboration with architects and package/platform teams.
• Estimate die-area, define optimal physical dimensions considering product costs, reticle limits, technology selection, metal stack, and reuse from product families.
• Drive execution and supervise progress of smaller blocks/sub-systems, influencing placement, shape, channel planning for best area and convergence.
• Plan short/long-term schedules, understanding dependencies across top-level, block place/route domains.
• Collaborate with clock design and power delivery teams on physical block floorplans, tradeoffs for metal allocation.
• Drive methodologies, tools, best practices for streamlined floorplan physical design delivery.

Requirements

• Bachelor's in Electrical/Electronics/Computer Engineering with 4+ years relevant experience or Master's with 3+ years
• 3+ years using industry-standard EDA tools for floorplanning and APR
• 1+ years with Synopsys Fusion Compiler
• 4+ years with TCL, Python or Perl programming
• 2+ years with Calibre or ICV verification

Nice to have

• Knowledge of ASIC integration: floorplanning, clock/power distribution, global signal/I/O planning, macro placement
• Familiarity with hierarchical/top-down design, MIB handling, routing, physical convergence
• Deep knowledge of SoC floorplan: multi-voltage/clock domains, level shifters, thermal, die-to-die, package interactions
• Expertise in ICC2/FC, place/route flows, PD verification; large designs (20M+ gates, 2GHz+)
• Strong automation skills in tcl/perl/python; excellent communication/teamwork

Culture & Benefits

• Hybrid work model splitting time between on-site at assigned hirify.global site and off-site
• Competitive total compensation: pay, stock bonuses, health, retirement, vacation benefits
• Commitment to innovation, diverse teams, ethical hiring, RBA compliance