Design Engineering Architect (Memory Interface PHY)

TL;DR

Design Engineering Architect (Memory Interface PHY): Developing PHY architecture for memory interfaces with an accent on JEDEC standards, electrical timing, and power considerations. Focus on driving architecture decisions for high-speed IO and managing customer-facing technical engagements.

Location: San Jose, California

Salary: $178,500 – $331,500

Company

A global leader in electronic design automation (EDA) software and hardware tools for integrated circuit and system design.

What you will do

• Develop PHY architecture for memory interfaces (e.g., DDR, LPDDR) focusing on electrical, timing, and power requirements.
• Drive architectural decisions in alignment with JEDEC standards and compliance requirements.
• Act as the primary technical architect for customers during pre-sales, evaluations, and post-delivery support.
• Collaborate with Sales and Marketing teams to support RFIs and technical proposals.
• Work with design, verification, and silicon validation teams to ensure architectural intent is implemented.
• Influence product roadmaps by identifying future standards and customer-driven requirements.

Requirements

• M.S. degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum 15 years of industry experience in memory interface PHY or high-speed IO.
• Deep expertise in JEDEC standards and memory interface protocols.
• Proven experience owning customer-facing technical engagements and driving issues to closure.
• Excellent written and verbal communication skills.

Culture & Benefits

• Comprehensive medical, dental, and vision insurance options.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• Paid vacation and paid holidays.