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1 день назад

Advanced Packaging Design Staff Engineer

121 000 - 179 040$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR

Advanced Packaging Design Staff Engineer (Semiconductors/AI): Leading small project teams to deliver innovative packaging solutions for high-performance computing, AI, and networking with an accent on signal integrity, power delivery networks, and advanced 2.5D/3D technologies. Focus on optimizing multi-chip configurations, ensuring manufacturability, reliability, and performance trade-offs.

Onsite: Burlington, VT; Westborough, MA; or Boise, ID. Must be eligible for U.S. export-controlled information access (U.S. citizens, permanent residents, or protected individuals).

Salary: $121,000 - $179,040 per annum (USD)

Company

hirify.global develops semiconductor solutions for data infrastructure in enterprise, cloud, AI, and carrier architectures.

What you will do

  • Lead small project teams of design and simulation engineers to deliver high-quality packaging solutions.
  • Interface with package suppliers to select technologies ensuring manufacturability, performance, reliability, and cost.
  • Design substrates and boards considering electrical, mechanical, thermal requirements, and design for manufacturing.
  • Optimize signal shielding, power distribution, pinouts for package and system needs.
  • Collaborate with chip design and simulation teams on signal/power integrity.
  • Contribute to tool, process, and flow development, including library maintenance.

Requirements

  • Locations: Burlington, VT; Westborough, MA; Boise, ID (onsite)
  • U.S. export control eligibility required (U.S. citizen, permanent resident, or protected individual)
  • Bachelor’s in electrical engineering or related; 5+ years experience (Master’s/PhD preferred).
  • Experience in substrate/board design, design for manufacturing/reliability, electrical performance trade-offs.
  • Proven leadership of complex cross-functional projects.
  • Basic Cadence Allegro (3DIC/ISP/APD/SiP); understanding of HBM, DDR, SerDes, PCIe, Ethernet.
  • Knowledge of signal/power integrity and advanced packaging (CoWoS, EMIB, CPO, CPC).

Nice to have

  • Familiarity with Cadence Sigrity/Clarity/Innovus/Virtuoso, Ansys, AutoCAD, SolidWorks.
  • Running/interpreting signal/power simulations.
  • Strong communication for global stakeholders.

Culture & Benefits

  • Comprehensive benefits: financial well-being (employee stock purchase), family support, mental/physical health resources, recognition awards.
  • Opportunity to work on innovative, industry-leading packaging technologies.
  • Global collaboration across time zones.

Hiring process

  • Interviews evaluate experience, thought process, communication (no AI tools allowed).
  • Contact HR for accommodations.

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