ADCE Packaging Design Architect (Semiconductor)

TL;DR

ADCE Packaging Design Architect (Semiconductor): Defining and implementing strategies to optimize product performance and cost through advanced packaging technologies with an accent on substrate design, silicon bridges, and interposers. Focus on driving end-to-end development from concept to tapeout and optimizing silicon package board performance.

Location: Hybrid; must be based in Phoenix, Arizona or Hillsboro, Oregon (US)

Salary: $256,050 - $361,480 USD

Company

hirify.global is a global leader in semiconductor manufacturing and foundry services, developing cutting-edge silicon and packaging technology for the AI era.

What you will do

• Drive end-to-end substrate design from concept through tapeout, including physical layout and routing.
• Perform substrate fit and routing studies to establish design, performance, and cost tradeoffs.
• Collaborate with silicon and hardware teams to optimize silicon package board performance and pinout.
• Define substrate design rules, conduct reviews, and resolve DRCs to optimize package design.
• Maintain technical documentation and collateral within the product lifecycle management system.

Requirements

• Ph.D. or Master’s degree in Electrical, Chemical, or Mechanical Engineering, or Material Science.
• 10+ years of in-depth experience in Package, PCB design, or IC digital design.
• Proficiency with electromagnetic simulation tools such as Mentor, Cadence, SPICE, and Ansys.
• Expertise in Cadence Allegro (PCB Editor, APD/SiP, Sigrity) or Mentor Xpedition platform tools.
• Strong analytical skills for identifying, isolating, and debugging complex hardware issues.

Culture & Benefits

• Hybrid work model allowing a split between on-site and off-site work.
• Total compensation package including competitive pay and stock bonuses.
• Comprehensive benefit programs covering health, retirement, and vacation.
• Opportunity to contribute to state-of-the-art semiconductor manufacturing for the AI era.