Chiplet Physical Design Engineer (AI)

TL;DR

Chiplet Physical Design Engineer (AI): Designing and integrating multiple chiplets into a System-in-Package (SiP) with an accent on synthesis and place-and-route for high-speed CPU core designs. Focus on achieving timing and power convergence on advanced process nodes (3nm and below) to deliver high-performance AI silicon.

Location: Remote, based out of the United States

Compensation: $100k - $500k

Company

hirify.global is leading the industry on cutting-edge AI technology, developing high-performance RISC-V CPUs and AI platforms to redefine computing paradigms.

What you will do

• Design and integrate multiple chiplets into a System-in-Package (SiP) solution.
• Own critical aspects of synthesis and place-and-route for high-speed CPU core designs.
• Optimize performance, power, and area (PPA) outcomes on advanced process nodes.
• Collaborate with global experts across the USA, Japan, and other sites to deliver world-class silicon.
• Influence physical design methodologies and provide mentorship to other engineers.

Requirements

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
• 10+ years of industry experience in physical design for CPU or GPU products.
• Strong hands-on experience with Synopsys and/or Cadence tools across synthesis, P&R, and closure.
• Proven expertise in timing closure, ECO flows, and PV convergence at block and chip level.
• Proficiency in TCL scripting; Python or similar is strongly preferred.
• Must be based in the United States and eligible to access U.S. export-controlled technology.

Culture & Benefits

• Highly competitive compensation package and comprehensive benefits.
• Opportunity to work on cutting-edge RISC-V CPU technology from scratch.
• Collaborative environment that values curiosity and a commitment to solving hard problems.
• Interaction with a diverse global team of technologists.
• Equal opportunity employer.