Physical Design Engineer - STA (AI)

TL;DR

Physical Design Engineer - STA (AI): Driving static timing analysis and closure for complex, high-performance RISC-V CPU and AI SoC designs with an accent on timing paths, constraints, and optimization strategies. Focus on debugging SDC constraints, creating ECOs, and developing automation scripts to ensure chip performance across various corners and modes.

Location: Hybrid: Must be based in Austin, TX, Fort Collins, CO, or Santa Clara, CA

Salary: $100k - $500k

Company

hirify.global is leading the industry on cutting-edge AI technology, developing high-performance RISC-V CPUs and AI platforms.

What you will do

• Drive static timing analysis (STA) and closure for complex, high-performance designs.
• Collaborate with logic, DFT, and physical design teams to debug constraints and optimize paths.
• Ensure chips meet performance targets across various corners and modes.
• Develop scripts and methodologies to improve timing closure workflows.
• Influence chip performance through timing methodology innovation and automation.

Requirements

• 7+ years of industry experience with a proven record of successful tapeouts.
• Deep knowledge of STA tools and techniques, including noise, crosstalk, and OCV analysis.
• Proficiency in writing and debugging SDC constraints and creating ECOs.
• Strong scripting skills in Python, Perl, and TCL for flow development.
• Familiarity with SPICE modeling and worst-case corner analysis.
• Must be eligible to access U.S. export-controlled technology.

Culture & Benefits

• Highly competitive compensation package and benefits.
• Collaborative environment valuing curiosity and commitment to solving hard problems.
• Opportunity to work with world-class engineers on modern sub-micron process technologies.
• Hybrid work model.