High Speed AI Interconnect Signal Integrity Engineer (AI)

TL;DR

High Speed AI Interconnect Signal Integrity Engineer (Hardware/AI): Designing and validating high-bandwidth interconnect solutions for large-scale AI clusters with an accent on copper and optical technologies for next-generation inference and training systems. Focus on performing link and channel budget analysis, qualifying reliability for 100G–1.6T links, and optimizing SI margins across diverse media.

Location: On-site in Santa Clara, CA, Austin, TX, or Toronto, Canada

Salary: $100k - $500k

Company

hirify.global is a leader in cutting-edge AI technology, developing high-performance RISC-V CPUs and comprehensive AI platforms to redefine computing paradigms.

What you will do

• Define and specify high-speed interconnect architectures for large AI clusters.
• Develop requirements, validation plans, and test strategies for copper cables and optical transceivers (100G to 1.6T).
• Perform detailed link and channel budget analysis, including loss, jitter, eye margin, and BER across PVT and aging.
• Lead qualification and reliability testing, including accelerated life testing and failure analysis.
• Collaborate across hardware, systems, and manufacturing teams to ensure DFM/DTM optimization.
• Interface with industry suppliers to align system designs with future interconnect capabilities.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering.
• 5+ years of experience in high-speed communications (100G–1.6T) and signal integrity.
• Hands-on expertise with SI tools and lab equipment (Keysight ADS, VNAs, TDRs, BERTs, protocol analyzers).
• Experience with cable specification, testing, and mating life analysis.
• Must be eligible to access U.S. export-controlled technology (EAR compliance).
• Must be able to work on-site in Santa Clara, CA, Austin, TX, or Toronto, Canada.

Culture & Benefits

• Highly competitive compensation package.
• Environment focused on collaboration, curiosity, and solving hard technical problems.
• Opportunity to work with a diverse team of technologists building a high-performance RISC-V CPU from scratch.
• Equal opportunity employer.