SOC Emulation Engineer (AI)

TL;DR

SOC Emulation Engineer (Hardware Emulation): Supporting hardware emulation infrastructure and internal chip design teams with an accent on integrating transactors and developing Python-based test frameworks. Focus on bridging the gap between hardware RTL and software drivers and triaging full-stack issues from Python tests down to hardware.

Location: Hybrid based in Austin, TX or Santa Clara, CA. Candidates must be eligible to access U.S. export-controlled technology (e.g., citizenship, permanent residency, or license).

Compensation: $100k - $500k including base and variable targets.

Company

hirify.global is a leader in cutting-edge AI technology, developing a high-performance RISC-V CPU to redefine the computing paradigm.

What you will do

• Integrate vendor and custom hardware transactors into RTL testbenches, managing clock domains and tri-state resolution.
• Develop Python-based test frameworks and APIs using pybind11.
• Maintain CMake-based compilation flows for emulation libraries.
• Provide technical support to internal chip design teams across multiple projects.
• Triage and debug the full stack, spanning from Python tests and C++ bindings to hardware.
• Utilize Synopsys Zebu for massive-scale silicon validation.

Requirements

• Degree in Electrical/Computer Engineering or Computer Science.
• 1-3 years of experience in chip design, verification, or emulation.
• Proficiency in Python for automation, working knowledge of C++, and ability to navigate SystemVerilog RTL.
• Solid understanding of standard chip interfaces, bus protocols, and hardware synchronization.
• Must be eligible to access U.S. export-controlled technology per EAR regulations.

Nice to have

• Experience using modern AI tools (Claude, ChatGPT, Copilot) to accelerate code generation and debugging.

Culture & Benefits

• Highly competitive compensation package.
• Opportunity to work on world-class RISC-V AI platforms.
• Collaborative environment dedicated to solving complex hardware-software problems.
• Exposure to industry-leading silicon validation platforms.