Senior Staff SoC Design Engineer (AI)

TL;DR

Senior Staff SoC Design Engineer (AI): Developing high-performance SoC microarchitecture and RTL for data center infrastructure with an accent on interconnect bandwidth, memory controllers, and system-level integration. Focus on delivering complex designs to tape-out, optimizing PPA targets, and collaborating across cross-functional teams to enable next-generation AI accelerators.

Location: Must be based in Santa Clara, CA

Salary: $134,390–$201,300 per annum

Company

hirify.global is a leading semiconductor company providing essential data infrastructure solutions for enterprise, cloud, and AI architectures.

What you will do

• Define microarchitecture and develop SystemVerilog RTL for SoC-level components including interconnects and power management.
• Integrate processor clusters, memory controllers (HBM/DDR), and high-speed interfaces.
• Collaborate with verification teams to review test plans and resolve functional debug issues.
• Execute standard design checks such as lint, CDC, and RDC while defining timing constraints.
• Coordinate with IP and analog teams to integrate complex interfaces like UCIe and UALink.
• Improve integration workflows and provide technical guidance to engineering staff.

Requirements

• Must be eligible to access export-controlled information under U.S. law.
• Bachelor’s degree in CS/EE with 5-10 years of experience or Master’s/PhD with 3-5 years of experience.
• Proven track record of delivering complex SoCs to tape-out.
• Strong RTL design skills in SystemVerilog and SoC integration experience.
• Familiarity with AMBA protocols (AXI), clock/reset design, and timing constraints.
• Experience with Python or Tcl for design automation.

Culture & Benefits

• Comprehensive financial well-being programs including an employee stock purchase plan.
• Robust family support and work-life balance initiatives.
• Extensive mental and physical health resources.
• Recognition and service awards for professional contributions.