Physical Design Engineer: Die-to-Die Interface (RTL to GDSII) (AI)

TL;DR

Physical Design Engineer (AI): Driving Die-to-Die (D2D) physical implementation from RTL to GDSII for multi-die/chiplet architectures with an accent on high-speed interfaces and sign-off quality. Focus on closing timing, signal integrity, and power integrity for complex AI semiconductor platforms.

Location: Remote (must be based in the U.S.)

Salary: $100k - $500k

Company

hirify.global is leading the industry on cutting-edge AI technology, developing high-performance RISC-V CPUs and AI platforms.

What you will do

• Lead Die-to-Die (D2D) physical implementation and closure from netlist to tapeout.
• Own the full RTL-to-GDSII flow, including synthesis, floorplanning, P&R, CTS, and sign-off.
• Drive timing and verification, including full STA, SI analysis (crosstalk, IR drop), and DRC/LVS sign-off.
• Develop and maintain physical design methodologies and automation scripts using Tcl and Python.
• Collaborate with analog and full-chip teams to resolve interface, LEF/LIB, and integration issues.

Requirements

• 5+ years of ASIC Physical Design experience at advanced nodes (7nm or below) with multiple successful tapeouts.
• Expertise in high-speed interfaces such as D2D, PCIe, HBM, or SerDes.
• Proficiency with Synopsys, Cadence, and Mentor EDA tools for implementation and verification.
• Must be eligible to access U.S. export-controlled technology (EAR compliance).
• B.S./M.S. in Electrical Engineering, Computer Engineering, or a related field.

Culture & Benefits

• Competitive compensation package including base and variable targets.
• Full remote flexibility for candidates located within the United States.
• Opportunity to build cutting-edge AI hardware and RISC-V CPU architectures.
• Collaborative environment that values curiosity and solving hard technical problems.