Mixed Signal IC Layout Design Engineer (AI)

TL;DR

Mixed Signal IC Layout Design Engineer (AI/FinFET): Owning full-custom layout for high-performance analog and mixed-signal IP in advanced FinFET nodes with an accent on translating schematics into manufacturable layouts that meet aggressive performance and area targets. Focus on optimizing floorplans and routing for SoC integration and driving physical verification flows to closure.

Location: Remote, based out of North America

Salary: $100k - $500k (including base and variable compensation targets)

Company

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance and cost efficiency through the development of a high-performance RISC-V CPU platform.

What you will do

• Plan and implement full-custom analog/mixed-signal layouts for blocks including PLLs, VCOs, ADCs, DACs, LDOs, and high-speed I/O.
• Build optimized floorplans and routing to balance area, parasitics, matching, and congestion for block-level IP and SoC integration.
• Apply advanced layout techniques such as common-centroid, symmetric differential routing, and shielding to meet noise and accuracy specs.
• Run and debug DRC, LVS, ERC, DFM, and antenna checks using Synopsys ICV or Siemens Calibre.
• Collaborate with circuit designers to iterate layouts based on post-layout extraction and simulation.
• Develop layout methodology and automation scripts using Python, Tcl, or SKILL to improve team productivity.

Requirements

• 5+ years of experience delivering silicon in CMOS/FinFET nodes.
• Deep proficiency in Cadence Virtuoso (XL/GXL) or equivalent custom layout environments.
• Strong understanding of interconnect stacks and advanced-node rules, including multi-patterning and lithography constraints.
• Fluency in physical verification flows (Calibre, PVS, Assura) for DRC, LVS, ERC, and LPE/RC.
• Must be based in North America.
• Must be eligible to access U.S. export-controlled technology (compliance with EAR).

Nice to have

• Experience in advanced FinFET nodes (7/5/3 nm).
• Experience with high-speed or RF-adjacent circuits such as SerDes, CDR, LNAs, or VCOs.
• Scripting proficiency in SKILL, Python, Tcl, or Perl.

Culture & Benefits

• Competitive compensation package and benefits.
• Collaborative environment that values curiosity and a commitment to solving hard problems.
• Opportunity to work with a diverse team on cutting-edge AI and RISC-V semiconductors.
• Equal opportunity employer.