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5 дней назад

Hardware/Silicon Internship (Silicon Engineering)

Формат работы
remote (только USA)/onsite
Тип работы
fulltime
Грейд
trainee
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Hardware/Silicon Internship (SystemVerilog/AI): Building and verifying production silicon for an energy-efficient general-purpose processor with an accent on RTL implementation, verification, physical design, and AI-assisted engineering tooling. Focus on defining micro-architecture, analyzing power-performance-area trade-offs, and finding issues before tapeout.

Location: On-site in Austin, TX, San Jose, CA, or Pittsburgh, PA for 12 weeks in Summer 2027; Fall 2027 options include full-time on-site, part-time on-site, or part-time remote work.

Company

hirify.global develops energy-efficient general-purpose processors for continuous AI/ML workloads and intelligent IoT devices.

What you will do

  • Define micro-architecture for processor blocks and features and implement RTL in SystemVerilog.
  • Convert specifications into verification plans, build testbench components, and write and debug tests.
  • Run synthesis, place-and-route, and timing analysis while evaluating power, performance, and area trade-offs.
  • Improve design, verification, and implementation flows through automation and AI-assisted tooling.
  • Collaborate with architecture, design, and verification engineers to identify and resolve issues before tapeout.

Requirements

  • Currently pursuing a BS, MS, or PhD in Electrical Engineering or Computer Engineering, with graduation expected by Summer 2028.
  • At least one academic term remaining after Summer 2027.
  • Coursework or project experience in digital logic design, verification, VLSI/physical design, or EDA tooling.
  • Experience with at least one programming or scripting language, such as Python, C/C++, Tcl, or Perl.
  • Ability to work on-site during the 12-week Summer 2027 internship in Austin, San Jose, or Pittsburgh.

Nice to have

  • Coursework in computer architecture.
  • Verilog or SystemVerilog proficiency.
  • Experience with synthesis, static timing analysis, place-and-route tools, simulators, or waveform debugging.
  • FPGA design experience.
  • Interest in applying LLMs or agents to engineering workflows.

Culture & Benefits

  • Each intern owns a well-scoped project and works with a dedicated mentor.
  • Interns present their results to the engineering team at the end of the internship.
  • Competitive compensation and benefits package.
  • 401K match, company-paid benefits, equity program, and paid parental leave.
  • Flexibility and support for personal and professional development.

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