Physical Design Engineer (ASIC)

TL;DR

Physical Design Engineer (ASIC): Managing ASIC top-level floorplanning and integration for next-generation AI and PCIe switch products with an accent on physical design methodologies from RTL to tapeout. Focus on resolving complex chip-level integration issues, developing floorplan strategies, and collaborating with cross-functional teams to ensure silicon performance.

Location: Must work in person at our San Jose, USA site

Salary: $120,000–$192,000

Company

hirify.global is a global technology leader that designs, develops, and supplies a broad range of semiconductor and infrastructure software solutions.

What you will do

• Own chip floor planning, partition creation, and clock tree delivery for top-level partitions.
• Resolve physical design issues related to chip integration and assembly.
• Manage cross-functional interactions with the package team regarding I/O and bump planning.
• Develop and improve floorplan methodologies using industry-standard and internal tools.
• Perform technical evaluations of IPs and provide design specification recommendations.

Requirements

• Bachelor’s with 8+ years or Master’s with 6+ years of experience in top-level floorplanning.
• Expertise in die size estimation, partitioning, clocking, and pin assignment.
• Proven track record with bump planning, RDL routes, and multi-voltage domain designs.
• Strong experience resolving chip-level DRC/LVS/EMIR issues for advanced nodes.
• Proficiency in scripting languages such as Python, Tcl, or Perl.
• Must work in person at the San Jose site; no remote work is allowed.

Culture & Benefits

• Comprehensive medical, dental, and vision insurance plans.
• 401(k) participation with company matching.
• Employee Stock Purchase Program (ESPP) and equity award opportunities.
• Company-paid holidays, sick leave, and vacation time.
• Support for all applicable laws regarding Paid Family Leave and other leaves of absence.