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Senior Staff CAD Engineer (Multi-die 3DIC & Power)

127 630 - 191 200$
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Текст:
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TL;DR
Senior Staff CAD Engineer (Multi-die 3DIC & Power) (ASIC/CAD): Develop and maintain next-generation CAD flows and methodologies for multi-die design and power analysis with an accent on 2.5D/3D/3.5D die stacking, advanced packaging, and RTL-to-GDS implementation. Focus on automating CAD flows with TCL and Python, integrating EDA tools, and analyzing inter-die extraction, signal integrity, power, timing, and thermal behavior.

Location: Santa Clara, CA, United States. Applicants must be eligible to access technology and software subject to U.S. export control laws; export license review may be required before employment.

Salary: $127,630–$191,200 per annum

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, and carrier data infrastructure.

What you will do

  • Develop and maintain CAD flows and methodologies for multi-die design and power analysis across business units.
  • Deploy, support, and run regressions for CAD flows.
  • Collaborate with infrastructure teams to integrate flows into the broader CAD framework.
  • Explore agentic AI/ML tools and projects for CAD automation.
  • Engage weekly with external partners and internal customers on product requirements and EDA tool development.
  • Track industry trends, participate in industry events, and contribute to methodology and workflow innovation.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 5+ years of relevant experience, or a Master’s degree/PhD with 3–5 years of experience.
  • 3+ years of hands-on physical design and flow development in an ASIC RTL-to-GDS environment.
  • Strong proficiency in TCL and Python scripting for CAD flow development.
  • Experience with multi-die design, including 2.5D/3D/3.5D die stacking, floorplanning, SOIC hybrid bonding, inter-die extraction, and multi-die analysis.
  • Experience with advanced packaging technologies such as CoWoS, EMIB, PIVR, and COUPE, plus interposer routing and SI/PI analysis.
  • Experience with power analysis, including RTL power estimation and optimization, clock-gating efficiency, ASIC block power, glitch power, and UPF.

Nice to have

  • Experience with 3DIC Compiler, Integrity 3DIC, Fusion Compiler, Innovus, PrimePower, PP-RTL, Empower, Joules, or PowerArtist.

Culture & Benefits

  • Agile environment focused on continuous learning, innovation, and collaboration.
  • Employee stock purchase plan with a two-year lookback.
  • Family support programs and mental and physical health resources.
  • Recognition and service awards.
  • Comprehensive benefits supporting financial well-being, family support, health, and recognition.

Hiring process

  • Interviews assess individual experience, thought process, and communication skills in real time.
  • Use of AI tools during interviews is prohibited unless explicitly authorized.

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