Назад
Company hidden
5 дней назад

Design Verification Engineer (EDI)

Формат работы
hybrid
Тип работы
fulltime
Грейд
middle/senior
Английский
b2
Страна
UK
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/

TL;DR

Design Verification Engineer (EDI): Participating in all aspects of digital verification for complete mixed signal IC developments, working on complex verification systems, and contributing towards improvements in verification methodology within hirify.global with an accent on delivering thoroughly verified ICs. Focus on creating reliable and reusable testbenches for complex subsystems and ICs, supporting the verification team, and hands-on project design/verification involvement.

Location: Must be based within commutable distance of Edinburgh or Newbury, UK, or willing to relocate prior to beginning employment.

Company

hirify.global solves complex challenges with innovative end-user solutions for the world's top consumer brands.

What you will do

  • Define IC verification plans linking product requirements through to detailed testcases.
  • Lead teams of verification engineers to deliver thoroughly verified ICs.
  • Create reliable and reusable testbenches for complex subsystems and ICs.
  • Participate in verification Specialist Groups and contribute to digital verification methodology discussions.
  • Support and coach the verification team to follow and improve defined methodology practices.
  • Hands-on project design/verification involvement.

Requirements

  • BEng / BSc / MEng / MSc Degree or equivalent in Electronics/Computer Science or other related discipline.
  • Proven track record in delivering 1st time success with complex mixed signal IC’s.
  • Experience with metric-driven verification, verification planning, and requirements extraction.
  • Experience with directed and constrained random verification, functional and code coverage analysis.
  • Proficiency in SystemVerilog and SVA (SystemVerilog Assertions).
  • Experience in testbench design with verification frameworks like UVM/OVM, e, VMM.
  • Strong debugging skills in RTL, Testbench, OOP, and Gate level (including SDF).
  • Strong ability to interpret results and resolve problems.
  • An innovative, creative, lateral thinking problem solver.

Nice to have

  • Formal verification and verification qualification techniques.
  • Scripting experience with Ruby, sh/csh, TCL, Make, Perl.
  • Power aware verification (using CPF/UPF).
  • Object-oriented programming (OOP) - Use of OOP design patterns.

Culture & Benefits

  • Personal and professional development opportunities.
  • Uniquely flat culture.
  • Commitment to encouraging an open and collaborative culture where different approaches, ideas, and points of view are respected and valued.
  • Promote a workplace where everyone can contribute irrespective of race, colour, national origin, religion or belief, gender or gender identity, sexual orientation, age, marital status, pregnancy status, or disability.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →