Principal Design Engineer (ASIC)

TL;DR

Principal Design Engineer (ASIC): Leading physical design implementation projects for advanced technology nodes with an accent on floorplanning, timing closure, and signoff verification. Focus on driving complex low-power and high-speed design methodologies and collaborating with RTL teams to ensure successful tapeouts.

Location: Must be based in Gyeonggi-do (Seoul), South Korea

Company

hirify.global is a global leader in electronic design and computational software, focused on helping innovators solve complex technology challenges.

What you will do

• Lead physical design implementation projects including floorplanning and power grid design.
• Execute place and route, clock tree synthesis, and timing closure.
• Perform physical, EM/IR, and DFM signoff verification.
• Develop and refine next-generation physical design methodologies and flows.
• Collaborate closely with RTL design teams to ensure high-quality, successful tapeouts.
• Provide technical leadership on challenging low-power and high-speed design projects.

Requirements

• 9+ years of experience with ASIC design flow and hierarchical physical design strategies.
• Deep understanding of sub-micron technology issues and physical verification processes.
• Solid knowledge of Low Power Design, DFT, and static timing analysis.
• Proficiency in EM/IR-Drop/crosstalk analysis and formal verification.
• Ability to work independently and hands-on at all levels of the design process.
• English communication skills required for team collaboration.