SoC/Subsystem Design Engineer (AI)

TL;DR

SoC/Subsystem Design Engineer (AI): Leading the architectural definition and RTL design of high-performance AI acceleration systems with an accent on system-level optimization and robust power management. Focus on driving cross-functional collaboration to ensure reliability from initial architecture through silicon bring-up and validation.

Location: Seongnam, South Korea (Onsite)

Company

hirify.global is a cutting-edge AI hardware company developing next-generation AI acceleration solutions.

What you will do

• Define the SoC architecture and lead RTL design for high-performance AI acceleration chips.
• Collaborate with verification, software, and backend teams to ensure seamless IP integration.
• Work with DSP engineers to bridge complex algorithms with hardware implementation.
• Drive silicon bring-up processes and conduct hardware/software debugging.
• Develop advanced clock and power control methodologies to enhance system robustness.

Requirements

• 10+ years of experience in high-complexity RTL design using SystemVerilog or Verilog.
• Proven track record leading SoC subsystem designs from concept to physical implementation.
• Expertise in simulation tools like VCS or Xcelium for complex debugging.
• Mastery of Lint, CDC, RDC, DFT, and Synthesis flows.
• Comprehensive understanding of the full SoC lifecycle including power-on sequences.

Nice to have

• Deep experience in designing and optimizing Clock, Reset, and Power Control Units.
• Understanding of ARM MMU architectures and memory coherency protocols.

Culture & Benefits

• Opportunity to work on next-generation AI acceleration hardware.
• Collaborative, high-reliability engineering environment.
• Exposure to full-stack silicon development from architecture to bring-up.

Hiring process

• Application review, followed by an online interview and an on-site interview.
• Culture-fit evaluation and final offer negotiation.