SoC/Subsystem Design Engineer (AI)

Location: On-site in Seongnam, Gyeonggi-do, South Korea

Company

hirify.global develops AI acceleration semiconductor systems.

What you will do

• Lead the architectural definition, RTL design, and system integration of SoCs and subsystems for high-performance AI acceleration.
• Collaborate with verification, software, backend, and DSP engineers to integrate IP and translate complex algorithms into hardware.
• Drive silicon bring-up, hardware/software debugging, and validation for mission-critical reliability.
• Design and apply advanced clock and power control methodologies to improve SoC robustness and resistance to environmental perturbations.

Requirements

• 10+ years of experience in high-complexity RTL design using SystemVerilog or Verilog.
• Experience leading SoC subsystem designs from conceptual architecture through physical implementation.
• Expertise with VCS or Xcelium, including complex RTL and gate-level simulation debugging.
• Mastery of lint, CDC, RDC, DFT, synthesis flows, and automated integration tools such as IP-XACT.
• Understanding of the full SoC lifecycle, including power-on reset sequences and clock-domain crossing.

Nice to have

• Experience designing and optimizing clock, reset, and power control units.
• Understanding of ARM MMU architectures and memory coherency protocols.

Culture & Benefits

• Cross-functional collaboration across hardware, verification, software, backend, and DSP teams.
• Hiring process includes document screening, online interview, on-site interview, culture-fit interview, compensation discussion, and final acceptance.