Physical Implementation Engineer - DFT

Location: On-site in Seongnam, South Korea

Company

hirify.global develops semiconductor hardware and AI-oriented chip products.

What you will do

• Insert and simulate logic/IP scan compression and plan DFT for SoCs.
• Implement and simulate Logic BIST and BIRA/BIST solutions.
• Plan package-level testing and implement DFD logic, including scan-dump and scan-to-DRAM paths.
• Support DFT activities from synthesis through production.
• Propose architectural and implementation changes to improve test and fault coverage.
• Support DSPs and contractors while maintaining turnaround time and result quality.

Requirements

• Bachelor's degree or higher in Electrical Engineering, or equivalent practical experience.
• At least 8 years of experience with EDA tool workflows in the semiconductor industry.
• Proficiency in Tcl, Perl, or Python for workflow automation and data visualization.
• Extensive experience with physical design processes and tools for automating RTL-to-GDS workflows.
• Strong understanding of advanced packaging, including 2.5D, 3D, and chiplet architectures.
• Experience leading aspects of physical implementation and analyzing design parameters and QoR trends.

Culture & Benefits

• Hiring process: document screening, online interview, on-site interview, culture-fit interview, compensation discussion, and final decision.
• The hiring process and schedule may vary depending on the role and circumstances.
• Applications may close early when the position is filled.