Physical Implementation Engineer (DFT)

TL;DR

Physical Implementation Engineer (DFT): Designing and managing Design-for-Test (DFT) strategies for complex AI SoCs with an accent on scan insertion, BIST implementation, and package-level test planning. Focus on optimizing test fault coverage, automating RTL-to-GDS workflows, and ensuring high-quality design implementation for next-generation semiconductor products.

Location: Seongnam, South Korea (On-site)

Company

hirify.global is an AI hardware company specializing in the development of high-performance semiconductor solutions for AI workloads.

What you will do

• Develop and execute comprehensive DFT strategies including logic/IP scan insertion and simulation.
• Implement Logic BIST and BIRA/BIST integration for robust SoC testing.
• Design DFD logic for scan-dump and scan-to-DRAM capabilities.
• Develop and refine implementation recipes to improve overall fault coverage.
• Lead physical design automation tasks from synthesis through to production.
• Collaborate with internal teams and external partners to maintain project timelines and quality standards.

Requirements

• Bachelor’s or higher degree in Electrical Engineering.
• Minimum 8 years of experience with EDA tool workflows in the semiconductor industry.
• Proficiency in scripting languages like Python, Tcl, or Perl for automation.
• Extensive experience in physical design processes and RTL-to-GDS workflows.
• Deep understanding of advanced packaging technologies including 2.5D, 3D, and chiplets.
• Demonstrated experience leading physical implementation aspects and analyzing design quality trends.

Hiring process

• Document screening, followed by online and on-site interviews.
• Culture-fit assessment, compensation negotiation, and final offer.