SoC/Top Design Engineer (AI)

TL;DR

SoC/Top Design Engineer (AI): Performing RTL integration and top-level design for complex SoC projects with an accent on system architecture, performance, and power optimization. Focus on integrating complex subsystems like NPU and memory interfaces while collaborating across verification and physical design teams to ensure design closure.

Location: Seongnam, South Korea (Onsite)

Company

hirify.global is an AI semiconductor company specializing in high-performance NPU architectures.

What you will do

• Perform SoC top-level architecture design and RTL integration.
• Integrate subsystems including CPU, AI, and memory interfaces with bus interconnects.
• Manage clock, reset, and power domain controls.
• Conduct synthesis, timing, and power analysis for performance optimization.
• Collaborate with backend and verification teams for tape-out processes.
• Support DFT and functional verification activities.

Requirements

• 5+ years of experience in RTL design and SoC integration.
• Proficiency in Verilog/SystemVerilog and AMBA (AXI/AHB) protocols.
• Knowledge of EDA tools and SoC design flows (Synthesis, P&R, STA, ECO).
• Strong analytical and problem-solving skills.
• Effective cross-team communication and collaboration.

Nice to have

• Experience in CPU/GPU/NPU IP integration.
• Expertise in low-power and high-speed design.
• Familiarity with UVM-based verification environments.
• Scripting skills in Python or TCL.
• Linux-based development environment experience.

Hiring process

• Document screening followed by online and on-site interviews.
• Culture-fit evaluation and final compensation negotiation.