Physical Design Engineer - Frontend

Location: On-site in Seongnam, Gyeonggi-do, South Korea

Company

hirify.global develops semiconductor hardware and related physical design solutions.

What you will do

• Implement and optimize physical design workflows from RTL to GDS for improved power, performance, and area.
• Conduct logic synthesis, including physically aware synthesis, clock-gating insertion, and feasibility checks for new architectures.
• Perform logic-equivalence checks, functional ECOs, static timing analysis, simulation, and setup/hold timing sign-off.
• Fix logic design-rule issues, estimate power consumption, and optimize PPA through PVT adjustments.
• Propose architectural changes to improve logical QoR and analyze design trends.
• Support DSPs and contractors in meeting turnaround-time targets while maintaining quality.

Requirements

• Bachelor’s degree or higher in Electrical Engineering, or equivalent practical experience.
• At least 8 years of experience with EDA tool workflows in the semiconductor industry.
• Extensive experience with physical design processes and tools for automating RTL-to-GDS workflows.
• Proficiency in Tcl, Perl, or Python for workflow automation and data visualization.
• Strong understanding of in-place optimization during ECO and experience leading aspects of physical implementation.
• Experience extracting design parameters, summarizing QoR, and analyzing trends to improve results.

Culture & Benefits

• On-site work at the R-TOWER office in Seongnam, South Korea.
• Structured hiring process with online, on-site, and culture-fit interviews.

Hiring process

• Application review.
• Online interview, on-site interview, and culture-fit interview.
• Compensation discussion followed by final hiring decision.