Physical Design Engineer (Frontend)

TL;DR

Physical Design Engineer (Frontend): Implementing physical design processes from RTL to GDS to achieve optimal performance, power, and area with an accent on logic synthesis, timing sign-off, and ECO workflows. Focus on improving design Quality of Results through architectural proposals, workflow automation using scripting, and managing complex physical implementation challenges in the semiconductor industry.

Location: Onsite in Seongnam, South Korea

Company

hirify.global is an AI semiconductor company focused on developing high-performance hardware solutions.

What you will do

• Implement physical design processes from RTL to GDS to achieve optimal PPA.
• Conduct logic synthesis, clock-gating insertion, and feasibility checks for new architectures.
• Perform STA, simulation, and logic equivalence checks for design sign-off.
• Manage setup/hold timing sign-off and fix logic design rules.
• Estimate power consumption and optimize PPA, including PVT adjustments.
• Support design teams and contractors to ensure high-quality, timely delivery.

Requirements

• Bachelor’s or higher degree in Electrical Engineering.
• Minimum of 8 years of experience with EDA tool workflows in the semiconductor industry.
• Proficiency in scripting languages like Tcl, Perl, or Python for automation and data visualization.
• Extensive experience in physical design processes and automating RTL to GDS workflows.
• Strong understanding of In-Place-Optimization during ECO and physical implementation.
• Proven ability to analyze QoR trends and extract design parameters for performance improvement.

Hiring process

• Document screening followed by online and on-site interviews.
• Culture-fit interview and compensation discussion.